module top;

wire A,B,C,D,E,OUT1,OUT2,OUT3,OUT4,OUT5,F;

system_clock#1600 clock(A);

system_clock#800 clock(B);

system_clock#400 clock(C);

system_clock#200 clock(D);

system_clock#100 clock(E);

not a1(OUT1,A);

and a2(OUT2,OUT1,B);

or a3(OUT3,C,D);

not a4(OUT4,OUT3);

and a5(OUT5,OUT4,E);

or a6(F,OUT2,OUT5);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule