10.14

module top;
wire OUT, OUT1, A1, B1, SEL, A0, B0;
system_clock #1600 clock1(A1);
system_clock #800 clock2(A0);
system_clock #400 clock3(SEL);
system_clock #200 clock4(B1);
system_clock #100 clock5(B0);

mux M1(OUT1, A1, B1, SEL);
mux M2(OUT0, A0, B0, SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

and a1(sel_1, A, SEL);

not n1(sel_n, SEL);

and a2(sel_2, B, sel_n);

or OUT(OUT, sel_1, sel_2);

endmodule


module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>5000)$stop;

endmodule